pipelined

The model is an abstraction of parallel systems that use digital electronic processors and optical pipelined buses for communication.

该模型是一个用于通信的数字处理器和光学电子流水线总线并行系统的抽象。

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic.

这款双通道ADC内核采用多级、差分流水线架构，并集成了输出纠错逻辑。

Indicates whether the ServicePoint object supports pipelined connections.

指示ServicePoint对象是否支持管线连接。

Graph Process Unit(GPU) usually adopts a pipelined architecture, and implements some general computer graphics API.

图形处理器（GPU）通常采用流水线体系结构，遵循通用图形接口规范。

Due to its high precision and high sampling rate, research and design on pipelined ADC are widely attention to.

由于具有高精度和高采样速率等优点，流水线结构ADC的研究和设计引起了广泛关注。

Examples of pipelined operations are projections, selections, and joins.

管道操作的示例是映射、选择和联接。

This allows pipelined execution, in the typical manner adopted by relational database systems.

这允许按关系数据库系统采用的典型方式进行流水线执行。

Each stream processor has a fully pipelined integer arithmetic logic unit (ALU) and floating point unit (FPU).

每一个流处理器有一个全面的流水线整数算术逻辑单元（ALU）和浮点单元（FPU）。

The segments are then pipelined to the close-pair identification component.

该片段，然后流水线就要结束对鉴定的组成部分。

This information is pipelined down to the page handler through the HttpContext object.

这些信息通过HttpContext对象传递给页面处理程序。

Pipelined level one instruction cache (PIL1) has been proposed to improve instruction fetch bandwidth in high frequency processor.

流水化的指令缓冲存储器通常被用于高频率处理器中，以提高取指带宽。

The data paths are internally pipelined to achieve very high bandwidth.

数据途径国内流水线，完成十分高地带宽。

The paper describes the principle, design and implement of Pipelined digital signal generator based on VME BUS.

介绍了基于VME流水线数字信号产生器工作原理、设计与实现过程。

The design is fully pipelined for maximum throughput.

设计采用了流水线以提供最高的吞吐量。

Therefore, this MDAC can reduce capacitor mismatching error by CFCS and fulfill the requirement of 12-bit 100MSPS pipelined ADC.

研究结果表明，本MDAC能通过CFCS技术抑制电容失配误差，并达到了12位100MSPS流水线ADC的指标要求。

This tip has demonstrated the use of the event-based API of StAX for pipelined XML applications, such as the merging of documents.

这篇技巧示范了在管道式XML应用程序中使用StAX的基于事件的API，比如文档的合并。

The pipelined approach is much quicker.

流水线操作方法要快得多。

There are no pipelined delays associated with the part.

该器件无流水线延迟。

A Pipelined Carry-dependent Sum Adder with its Self-checking Structure

基于流水线的自检测进位相关和加法器设计

Design and Analysis of a high-speed Comparator in a pipelined ADC

流水线ADC中高速比较器的设计和分析